2016中国国际半导体技术大会(CSTIC)
会议介绍
Plenary Session
CSTIC 2016, Sunday, March 13, 2016
SHICC Shanghai International Convention Center
No.2727 Riverside Avenue Pudong, Shanghai 200120, China
08:45–09:35
OpeningCeremony,
OpeningRemarksbyConferenceChair
OpeningRemarksbySEMI
OpeningRemarksbyECS
OpeningRemarksbyChineseGovernmentRepresentatives
PresentationofECSBestStudentPaperAwardsandSEMIBestYoungEngineerPaperAwards
MeetingRoom
3rdFloorAuditorium
09:35–10:20
Dr.BENEDETTOVIGNA
ExecutiveVicePresident,GeneralManager,Analog,MEMS&SensorsGroup,STMicroelectronics
10:20–10:40
CoffeeBreak
10:40–11:20
Dr.Chia-HongJan
IntelFellowanddirectorofsystem-on-chip(SoC)technologyintegrationfortheTechnologyandManufacturingGroup
11:20–12:00
QingChu
Vicepresident,HuaweiTechnologiesCo.,Ltd.
12:00–13:30
7thFloorGrandBallroom1
ParallelSymposiumOralSessions
Sunday,March13,2016
13:30–17:00
ParallelSymposiumOralSessions,
17:00–18:30
ConferencePosterSession,
Monday,March14,2016
8:00-18:00
ParallelSymposiumOralSessions,
JointSessions
SymposiumIIandSymposiumIII-Lithograpy/Etchjointsession
Sunday,March13,2016
ShanghaiInternationalConventionCenter
MeetingRoom:TBD
SessionChairs:KafaiLai(IBM)andYingZhang(Applied)
13:30-13:35
OpeningRemarks
KafaiLai/YingZhang
**13:35-14:05
Moore'sLaw:NoEndinSight
VivekSingh,Intel
**14:05-14:35
AtomicLevelPrecisionMaterialsEngineering
PeterLoewenhardt,AppliedMaterials
**14:35-15:05
Developmentof250WEUVlightsourceforHVMlithography
Mizoguchi,Giaphoton
**15:05-15:35
MaterialsInnovationforCost-EffectiveLithography
RalphDammel,EMD/AZ
15:35-15:50
CoffeeBreak
SymposiumIIandSymposiumXI-DTCOJointsession
Monday,March14,2016
ShanghaiInternationalConventionCenter
MeetingRoom:TBD
Sessionchairs:LeoPang/YiyuShi
*8:30-8:35
OpeningRemarks
LeoPang/YiyuShi
**8:35-9:05
NanolithographyandDesignTechnologyCo-optimizationinExtremeScaling
DavidPan,UTAustin
**9:05-9:35
Wearable&ImplantableMedicalapplication–achallengetointegratedRFtransceiverdesign
ZhihuaWang,TsinghuaUniversity
**9:35-10:05
TheNextFrontierinICDesign:Determining(andOptimizing)RobustnessandResilienceofIntegratedCircuitsandSystems
Dr.-Ing.UlfSchlichtmann,TechnicalUniversityofMunich
10:05-10:20
CoffeeBreak
主题演讲和受邀者（2016）
Keynote & Invited Speakers(2016)
Plenary Session
Dr. BENEDETTO VIGNA,Executive Vice President,General Manager, Analog, MEMS & Sensors Group,STMicroelectronics
Dr. Chia-Hong Jan,Intel Fellow and director of system-on-chip (SoC) technology integration for the Technology and Manufacturing Group
Qing Chu,Vice president,Huawei Technologies Co., Ltd.
Confirmed Invited Speakers
** Keynote Speech * Invited Speech
Symposium I: Device Engineering and Technology
*Gary Bronner, Rambus
*Changhwan Choi, Associate Professor, Hanyang Universiy
The Effects of Materials and Process on the Electrical Characteristics of Tunneling FETs
*Moon-Ho Ham, Professor, Gwangju Institute of Science and Technology
Engineering Graphene for Transistors and Interconnects
*Yu Hao, Professor, Nanyang Technological University
Future Brain-like Computing with Non-volatile Memory Device
*Jan Hoentschel, GLOBALFOUNDRIES
*Sunkook Kim, Professor, Kyung Hee University
Flexible 2D Semiconducting Electronics
*Chung Lam,DE and Manager, IBM, USA
Memory Devices in Computing
*Juin J. Liou, Professor, University of Central Florida
Compact Modeling of Junction Failure in Semiconductor Devices Subject to
Electrostatic Discharge Stresses
*Ming Li, Peking University
Gate and source/drain engineering in Ge device technology
*Zhitang Song, SIMS CAS
*Hitoshi Wakbayashi, Tokyo Institute of Technology
*Jianhua Joshua Yang, Professor, University of Massachusetts
Memristor Mates enable memory and neuromorphic applications
*Qingtai Zhao, Forschungszentrum Jülich
Symposium II: Lithography and Patterning
**Vivek Singh, Director, Fellow,Intel
Moore's Law: No End in Sight
**Mizoguchi, CTO, Gigaphoton
Development of 250W EUV light source for HVM lithography
**David Pan, Professor, U Texas at Austin
Nanolithography and Design Technology Co-optimization in Extreme Scaling
*Edmund Lam, Professor, HKU
Impact of photomask shape uncertainties on computational lithography
*Leo Pang, VP, D2S
Latest Progress of Model-based Mask Data Preparation for OPC and ILT at 10nm Node and Beyond
**Wang Yueh, Principal Engineer, Intel
HVM materials for Sub-10nm nodes
**Peter Trefonas, Corporate Fellow, Dow Chemical
Moore or Less? The Map Grows Increasingly Complex as Materials and Processes Abound
*Rikimaru Sakamoto, R&D Manager, Nissan Chemical Industries, LTD.
Dry Development Rinse Process (DDRP) and Material (DDRM)
*Takeshi Kato, Senior Engineer, Hitachi High-Technologies Corporation
Advanced CD-SEM metrology for Edge Placement Error (EPE) control at the15 nm node and beyond
*Lixian Yu, Research staff member, Institute of Microelectronics, CAS
Layout Decomposition for MPT and Lithography Simulation
*Xiaojing Su, Yingli Duan, Research staff member, Institute of Microelectronics, CAS
Design technology co-optimization for N14 Metal1 Layer
**Peter Loewenhardt, VP, Applied Material, USA
Atomic Level Engineering
**Dr.-Ing. Ulf Schlichtmann, Professor, Technical University of Munich
The Next Frontier in IC Design: Determining (and Optimizing) Robustness and Resilience of
Integrated Circuits and Systems
**Zhihua Wang, Professor of Electronic Engineering, Deputy Director of the Institute of Microelectronics, Tsinghua University, Chairman of IEEE Solid-State Circuit Society Beijing Chapter,an official member of China National Commission of URSI
Wearable & Implantable Medical application – a challenge to integrated RF transceiver design
**Ralph Dammel, EMD
Materials Innovation for Cost-Effective Lithography
*Chiaki Kato, Tohoku University
MEMS’s technology trend
*Hidetami Yaegashi, Senior member of technical staff, TEL
Pattern Fidelity control in Multi-patterning towards 7nm node
Symposium III: Dry & Wet Etch and Cleaning
*Rich Wise, Managing Director, Lam Research, USA
Patterning Technology Inflections for the 10nm, 7nm and 5nm Logic Nodes
*Peter Loewenhardt, VP, Applied Materials, USA
Atomic Level Engineering
*Steven Scheer, Senior Manager, TEL
Patterning Challenges for N7 and Beyond
*Leonid Dorf, Senior MTS, Applied Materials, USA
Low Electron Temperature Etch Chamber (LETEC) for Atomic Precision Etching
*Maxime Darnon, Professor, Université de Sherbrooke, Canada
Plasma etching for High Efficiency Solar Cells fabrication
*Tom Ni, VP, AMEC, China
Dielectric Etch challenges and Solutions for Advanced Nodes
*Marc Zelsmann, Research Scientist, CNRS, France
A route for industry-compatible DSA of high-chi PS-PDMS block copolymers
*Dr. Huixiong Dai, Director, Applied Materials, USA
Patterning Roadmap for Advanced Technology Nodes
*Shenjian Liu, Managing Director and deputy general manager, AMEC,China
Inductive Coupled Plasma Etch Development for 10nm and Beyond Technology Node
*Dr. Peter Ventzek, TEL
Control of Atomic Layer Reactions for Plasma Processing
**Vivek Singh, Director, Fellow, Intel
Moore's Law: No End in Sight
**Mizoguchi, CTO, Gigaphoton
Development of 250W EUV light source for HVM lithography
**Ralph Dammel, EMD
Materials Innovation for Cost-Effective Lithography
Symposium IV: Thin Film Technology
**Dr.Chris Penny, Snr Engineer, IBM
Challenges in BEOL (Back End of Line) Cu Integration at the 7nm Node and Beyond
*Dr.Tsann Lin, Principle Scientist, Development of p-MTJ stacks, IMEC
The Exploration of p-MTJ Stacks for STT-MRAM Devices
*Dr.Tae-gon Kim, Sr. researcher,Advanced film characterization & 3 dimensional structure characterization, IMEC
Metrology challenges in advanced semiconductor technologies
**Dr.Victor Zhirnov, Chief Scientist,Semiconductor Research Corporation
Scaling Limits of Nanoionic Devices
*Mr.Hao Deng, DCVD Manager, TD-SMIC
New applications and challenges of dielectric films at 14nm FinFET technology and beyond
*Dr.Jingmei Liang, Technology Director, DSM, CVD, AMAT
Flowable oxide: N10 STI Gapfill Challenges
*Dr.Xinyu Fu, Senior Manager of process engineering, MDP, AMAT
A Conformal Low Resistivity Fluorine Free Tungsten for FINFET Metal Gate and 3D Memory Applications
*Dr.Natalia Doubina, Snr process engineer, ECP, Lam Research
Application of Cobalt Electroplating for IC Interconnects
*Dr.Mikhail Baklanov, Principle Scientiest, IMEC
Innovative solutions for integration of ultralow-k materials for 10 nm technology nodes and beyond
*Yanqing Wu, Professor, HUST (Huazhong University of Science & Technology)
High Performance Electronics Based on Novel Two Dimensional Materials
*Peter M. ZAGWIJN, Senior Technical Product Manager, ASM International N.V.
ALD Nanolayers for Novel More than Moore Devices
**Zhenqiang Ma, Professor, University of Wisconsin at Madison, USA
Radio-Frequency Flexible and Stretchable Electronics
*Ning Cheng, Principal Engineer, Altera Corp.
Future FPGA - application, challenges and technology enablement
Symposium V: CMP, Wafer Substrate Polishing and Post-Polish Cleaning
**Dr. S.V. Babu, Professor, Clarkson University
Mitigation of corrosion challenges for barrier films at advanced nodes
*Dr. JH Han, Senior Member of Technical Staff, Global Foundries
Chemical Mechanical Polishing Innovation as a Key Technology for sub-10nm Logic Device
*Dr. Jin-Goo Park, Professor, Hanyang University
Adsorption and removal of BTA during Cu CMP and post Cu CMP cleaning
*Dr. Yufei Chen, Distinguished Member of Technical Staff, Applied Materials
Chemical Mechanical Cleaning for CMP Defect Reduction
*Dr. David Huang, Senior Technology Director, Pall
CMP Defect Reduction using Advanced Filtration Technology
*Junzhu Cao, Manager, SMIC
Copper CMP Dendrite Defect Investigation
*Dr. Charles Lin, Director, Dow Chemical
CMP consumable technology and solution addressing 28nm and beyond logic device CMP process challenges
*Jack Fong, Global Application Manager, Cabot Microelectronics
Advancement of Systematic Thinking to Solutions for CMP Applications: "One or More?"
*Dr. Song-Yuan Chang, Sr. VP, Uwiz
Flexible Solutions for Cu Interconnect Planarization and Post Planarization Cleaning
*Elbert Chou, Managing Director, Kinik
A Novel Platform for Next Generation Pad Conditioner and Performance
*TBD,Anji Microelectronics
*Kee Joon Oh, Principal Engineer, SK hynix
New Colloidal W Slurry Effects for Scratch Reduction in W CMP
*Chao-Chang Chen, Professor, Taiwan University of Science and Technology
Study on CMP of Glass Wafer with SiO2 Based Slurry for Trench-Glass-Via Interposer
Symposium VI: Materials and Process Integration for Device and Interconnection
*Zhaoyun Tang, IMECAS/XMC
Intergration and Devices for 3D-Nand
*Jing Xu, Institute of Microelectronics of Chinese Academy of Sciences
Back Gate Recovery for FDSOI Devices
**Dr.Chris Penny, Snr Engineer, IBM
Challenges in BEOL (Back End of Line) Cu Integration at the 7nm Node and Beyond
**Dr.Victor Zhirnov, Chief Scientist, Semiconductor Research Corporation
Scaling Limits of Nanoionic Devices
**Zhenqiang Ma, Professor, University of Wisconsin at Madison, USA
Radio-Frequency Flexible and Stretchable Electronics
*Ning Cheng, Principal Engineer, Altera Corp.
Future FPGA - application, challenges and technology enablement
Symposium VII: Packaging and Assembly(CPMT APM Joint Symposium)
**Tan Boo Wei, Group Engineering Manager, R&D Department, Carsem Semiconductor
Automotive QFN Packaging Solution
*Yifan Guo, VP, ASE Shanghai
Advance in Semiconductor Packaging Technologies for IOT
*Herb Huang, Sr. Director of Technology Development in 3DIC and Sensors, SMIC
Prospectus of Wafer Level 3D System Integration and Packaging Solutions beyond TSV
**John Yuanlin Xie, Director, Packaging Technology Research and Development, Altera Corp., San Jose, CA
Roadmap towards TSV-Free 2.5D Integration
*Daquan Yu, VP Technology, Tianshui Huatian
Development of 3D WLCSP Using Vertical Via Last TSV Technology
*YB Lin, Director, JCET
MIS
*Mark Huang, CTO, Speed
Development of Fingerprint Sensor Module Assembly
*Dr. Dongkai Shangguan, CMO, StatschippaC
Advanced Packaging Technologies for System Integration
*Dr.Daniel Shi, Director, ASTRI
3D Packaging for Power Electronics Application
*Dr.Jianwen Li, VP Technology, SJSemi
*M.L. Huang, Professor, Dalian University of Technology
Dominant effect of diffusion anisotropy in β-Sn grain on electromigration behavior of SnAgCu solder bumps
*Dr. Ken Lee, CTO, SIMMTECH
Form Factor and Cost-Driven Advanced Package Substrates for Mobile and IoT Applications
Symposium VIII: Metrology, Reliability and Testing
**Adit D. Singh, Professor of Auburn University, US,IEEE Fellow
Adaptive Testing: Addressing the “Zero Defect” IC Quality Challenge
*Ted Lunquist, CTO, DCG Systems, US
New Solutions to Find Defects that Matter
*Barry Linder, Research Staff Member,IBM T. J. Watson Research Center
Combined Ramp Voltage Stress and Constant Voltage Stress for Reliability Modeling from Individual devices to Complete Packaged Chips
*Harry H. Chen, Research Scientist, MediaTek, Taiwan
Upstream data analytics to optimize system test
Symposium IX: Emerging Semiconductor Technologies
*Dr. Hongsik Jeong, Professor, Yonsei University
High Density PCM Technology
*Dr. Kuan-Neng Chen, Professor, National Chiao Tung University
Research Advances of Low Temperature Bonding Technology in 3D Integration and Heterogeneous Integration
*Dr. Yi-Chia Chou, Professor, National Chiao Tung University
Forming new silicide heterostructures in semiconductor nanowires
*Dr. Sung Hyun Jo, Senior Fellow, Crossbar
Resistive RAM: Beyond Emerging Memory Technology
*Dr. Jung Heon Lee, Professor, Sungkyunkwan University (SKKU)
Ultrastable-Stealth Large Gold Nanoparticles with DNA Directed Biological Functionality
*Dr. Chul-Ho Lee, Professor, Korea University
Optoelectronics based on Two-dimensional Semiconductor Heterostructures
*Dr. Dohun Kim, Professor, Yonsei University
Recent progress in developing semiconductor quantum dot based quantum bits
*Dr. Wenqi Zhang, Director, National Center for Advanced Packaging (NCAP)
Optical receiver with Si photonics for high speed optical communication
*Dr. Chien-Hung Lin, Director, Kingyoup Optronics
Submicron Polymer Temporary Bonding with Ultra-Fast Laser Ablation Application in 3D Semiconductor Package
*Masaaki Kuzuhara, Professor, Graduate School of Engineering, University of Fukui
GaN-based Heterojunction FETs for Power Applications
*Yasuyuki Miyamoto, Professor, Department of Physical Electronics, Tokyo Institute of Technology
Steep slope devices with InGaAs channel for post Si CMOS application
*Dr. SangBum Kim, Research Staff Member, IBM T.J. Watson Research Center.
Neuromorphic computing based on emerging non-volatile memory devices
*Dr. Chung-Hsun Lin, Device Engineering, Advanced Technology Development, GLOBALFOUNDRIES
*Dr. Zhiqiang Wei, Chief Engineer, Panasonic
Projecting the Reliability for 40 nm Embedded ReRAM and beyond
*Dr. Carlo Reita, Director, Nanoelectronics Technical Marketing and Strategy, CEA LETI
Solution for nanoelectronics beyond the 7nm node
*Dr. Edward Y. Chang, Dean, International Colledge of Semiconductor Technology, National Chiao Tung University
Study On The Electrical Characteristics of In Situ PEALD-Passivated HfO2/In0.53Ga0.47As MOSCAP and MOSFET Structures
*Dr. Jihwan An, Professor, Seoul National University of Science and Technology
Symposium X: Advances in MEMS and Sensor Technologies
*Stella Kuei-Ann Wen , Professor and Vice Dean of R&D division, National Chiao Tung University,Hsinchu Taiwan, China
Integration of MEMS in existing IC lines: Toward Sensor and Microelectronics-system Integration for Life Enhancement
*Zai-fa Zhou,Professor, Deputy Director of Key Laboratory of MEMS of Ministry of Education,Southeast University
In situ test structures for material property of thin films in MEMS applications
*Jianfei Sun, Associate Professor, Southeast University, China
Magnetic field-controlled assembly of magnetic nanoparticles for potential biomedical application
* Xinxin Li, Prof. Director, State Key Lab of Transducer Technology,SIMIT- CAS, China
Cheaper or smarter: help MEMS chips leave the bloody road
* Herb Huang, Sr. Director of Technology Development in 3DIC and Sensors, SMIC, China
* Yeon Sik Jung, Professor, Korea Advanced Institute of Science and Technology (KAIST), Korea
Fast and Convenient Sensing of Molecules by Printed 3D Superlattice Nanostructures
* In Kyu Park, Professor, Korea Advanced Institute of Science and Technology (KAIST), Korea
Telexible and stretchable transducers based on functional nano composites
* TBD,MiraMEMS, China
* Dr. Hong Wan,QST Corp. China
9-Axis Motion Sensor
*Huikai Xie, Professor, University Florida, USA
A Palm-size Near Infrared Fourier Transform MEMS Spectrometer
Symposium XI: Circuit Design, System Integration and Applications
*Shu-Min Kathy Li , Professor, National Sun Yat-Sen University
Layout-Aware Optimized Pre-bond Silicon Interposer Test Synthesis
*Tsung-Yi Ho, Professor, National Tsing Hua University
Digital Microfluidic Biochips: Towards Hardware/Software Co-Design and Cyberphysical System Integration
*Dr.-Ing. Ulf Schlichtmann, Professor, Technical University of Munich
The Next Frontier in IC Design: Determining (and Optimizing) Robustness and Resilience of Integrated Circuits and Systems
*Haibao Chen, Assistant Professor, the Department of microelectronics, SJTU
Interconnect Reliability Modeling and Analysis for Multi-Branch Interconnect Trees
*Li Jiang, Assistant Professor, the Department of Computer Science & Engineering, Shanghai Jiaotong University
On Diagnosable and Tunable 3D Clock Network Design for Lifetime Reliability Enhancement
*Yuan Ji, Professor, Shanghai University
Stochastic logics for low cost and low power wearable applications
*Zhihua Wang, Professor of Electronic Engineering, Deputy Director of the Institute of Microelectronics, Tsinghua University, Chairman of IEEE Solid-State Circuit Society Beijing Chapter,an official member of China National Commission of URSI
Wearable & Implantable Medical application – a challenge to integrated RF transceiver design
*Ngai Wong, Associate Professor of EEE Department, the University of Hong Kong
Constructive Tensor Outer-Product Decompositions With Applications in Circuit Modeling and Simulation
*Dong Xiang, Full Professor of School of Software, Tsinghua University
Thermal-Aware Small-Delay Defect Testing in Integrated Circuits for Mitigating Overkill
*Hailong Yao, Assistant Professor, Department of Computer Science and Technology, Tsinghua University
Flow-Control Co-Design Methods for Flow-Based Microfluidic Biochips
*Zuochang Ye, Associate Professor, Institute of Microelectronics, Tsinghua University
Application of Machine Learning in Circuit Optimization and Yield Analysis
*Shouyi Yin, Professor, Tsinghua University
*Zhi-Liang Qian, Assistant Professor, Shanghai Jiaotong University
Network-on-Chips (NoCs) based Multicore System: Performance Modeling, Architecture Optimization and Applications
**David Pan, Professor, U Texas at Austin
Nanolithography and Design Technology Co-optimization in Extreme Scaling
Symposium XII: Si Materials and Photovoltaic
*Dan Hu, Sr. Analyst, IHS Solar
Current market for High Efficiency Solar Cells
*Ted Guo, General Manager,ENN
HJ solar Cell Manufacturing
*Nam-Gyu Park, Professor, Sungkyunkwan University
High Efficiency Perovskite Cells
*Wenjin Wang, Director, IEE CAS
Device Physics of PERC Solar Cells
*Frank Liu, Professor, Shaanxi Normal University
High Efficiency Perovskite Cells
*Jinyan Zhang, R&D Director, Hanergy
Recent Development Progress of High Efficiency Rear-emitter Heterojunction Solar Cells
*Ivan Gordon, Manager, IMEC
Epi- emitter solar cells
*DengYuan Song, CTO, Yingli
n-type High Efficiency c-Si Solar Cells
*Jinjyuan Chen, VP, Ideal Energy
PECVD for HJT
*LuLu Chen, VP, Archers
RPD for HJT
*Guoqiang Xing, CTO, CSI
PERC Solar cells
*Tadashi Yoshihara, Sr. Manager, ULVAC
Cat-CVD for HJ Solar Cells
*Yuepeng Wan, Manager, GCL
High quality n-type wafer
【会议门票】参会费（非会员）：
2016年3月1日前/ 3700元/人
2016年3月1日后报名/ 4200元/人
费用包含：包括所有会议，U-key礼品，接待会与程序（软拷贝）。
【会议通知】
由中国电子商会（CECC）与SEMI主办的2016 中国国际半导体技术大会（CSTIC 2016）将于2016年3月13-14日在上海国际会议中心举行，中国国际半导体技术大会（CSTIC）是一个最大的和最全面的年度中国半导体技术会议。
会议将涵盖半导体技术和制造业的各个方面,包括设备、设计、光 刻、集成、材料、过程和制造,以及新兴的半导体技术和硅材料的应用等。热点议题,如3D集成,III-V半导体、碳纳米电子、LED、微机电系统和光伏发电技术也将在大会被讨论。
会议名称：2016 中国国际半导体技术大会（CSTIC 2016）
会议时间：2016年3月13-14日
会议地点：上海国际会议中心，上海市浦东新区滨江大道2727号