会议介绍
中国国际半导体技术大会(CSTIC) 2017
China Semiconductor Technology International Conference (CSTIC) 2017
Plan now to participate at CSTIC 2017, one of the largest and the most comprehensive annual semiconductor technology conferences in China and Asia since 2000. Organized by SEMI and IEEE-EDS , co-organized by IMEC and ICMTIA(The Integrated circuit Materials Industry Technology Innovation Alliance), and co-sponsored by ECS, MRS and CEMIA(the China Electronics Materials Industry Association), CSTIC 2017 will be held March 12-13, 2017 in Shanghai, China, in conjunction with SEMICON China 2017. The conference will have ten symposia cover all aspects of semiconductor technology with focus on manufacturing and advanced technology, including detail manufacturing processes, devices design, integration, materials, and equipment, as well as emerging semiconductor technologies, circuit design, and silicon material applications. Hot topics, such as memory technology, 3D integration, MEMS and Photovoltaic Technology will also be addressed in the conference.
Date and Venue
March 12-13, 2017
Shanghai International Convention Center
上海国际会议中心 中国上海浦东滨江大道2727号
No.2727 Riverside Avenue Pudong, Shanghai 200120, China
| 08:45–09:30 | Opening Ceremony |
| Opening Remarks by Conference Chair | |
| Opening Remarks by SEMI | |
| Opening Remarks by IMEC | |
| Opening Remarks by Chinese Government Representatives | |
| Presentation of SEMI Best Student Paper Awards and SEMI Best Young Engineer | |
| Paper Awards | |
| Meeting Room | 3rd Floor Auditorium |
| 09:30 –10:10 | Prof.Hiroshi Amano |
| Nobel Laureate in Physics, 2014 | |
| Director, Center for Integrated Research of Future Electronics, Institute of Materials and Systems for Sustainability, Nagoya University | |
| 10:10–10:25 | Coffee Break |
| 10:25–11:05 | Dr.Tzu-Yin Chiu |
| CEO and Executive Director,Semiconductor Manufacturing International Corp.(SMIC) | |
| 11:05–11:35 | Dr.Jong Shik Yoon |
| Executive Vice President Foundry Business System-LSI,Samsung Electronics Co,LTD,Korea. | |
| 11:35–12:05 | Prof.Rao Tummala |
| Joseph.M Pettit Chair Professor in ECE and MSE Director, 3D Microsystems Packaging Research Center Georgia Research Alliance Eminent Scholar Georgia Institute of Technology, Atlanta, Ga, USA |
|
| 12:05–13:30 | 7th Floor Grand Ballroom 1 |
Panel Discussion
Sunday, March 12, 2017
Meeting Room: 3B
17:00-18:00
Moderator:
Panel Members:
Parallel Symposium Oral Sessions
| Sunday, March 12, 2017 | |
| 13:30 – 18:00 | Parallel Symposium Oral Sessions |
| Coffee Break | Conference Poster Session |
| Monday,March 13,2017 | |
| 8:00-18:00 | Parallel Symposium Oral Sessions |
Joint Sessions
Symposium II and Symposium III-Lithograpy/Etch joint session
Sunday, March 12, 2017
Shanghai International Convention Cente
Meeting Room: 3rd Floor Yellow River Hall黄河厅
Session Chairs: Kafai Lai (IBM) and Ying Zhang (Applied Material)
| 13:30-13:35 | Opening Remarks |
| Kafai Lai / Ying Zhang | |
| **13:35-14:05 | TBD |
| Donis Flagello, Nikon Research America | |
| **14:05-14:35 | Patterning Technology Inflections for the 10n and Beyond Logic Nodes |
| Rich Wise, Lam Research | |
| *14:35-14:55 | Development of 250W EUV light source for HConsiderations for pattern fidelity control towards 5nm nodeVM lithography |
| Hidetami Yaegashi, TEL | |
| *14:55-15:15 | The Insertion of extreme ultraviolet lithography (EUVL) from patterning perspective |
| Weimin Gao, Synopsys | |
| 15:15-15:30 | Coffee Break |
Symposium II and Symposium IX-DTCO Joint session
Monday, March 13, 2017
Shanghai International Convention Center
Meeting Room: 3rd Floor Yellow River Hall黄河厅
Session chairs: Leo Pang / Yiyu Shi
| *8:30-8:35 | Opening Remarks |
| Leo Pang / Yiyu Shi | |
| **8:35-9:05 | Design Technology Co-optimization for Disruptive Patterning Schemes |
| Puneet Gupta, UCLA | |
| **9:05-9:35 | TBD |
| Shaojun Wei, Tsinghua University | |
| *9:35-9:55 | TBD |
| Luigi Capodieci, Motovi.ai | |
| 9:55-10:10 | Coffee Break |
Partial list of other confirmed distinguished CSTIC 2017 invited speakers
| Advanced Logic and Specialty Technologies for VLSI Manufacturing in fast expansion at China |
| Min-hwa Chi, Sr, VP, SMIC |
| Steep-slope device |
| Dr., Qingtai Zhao, Forschungszentrum Julich |
| Reliability enhancement of phase change memory using metal nitride liner |
| Dr., SangBum Kim, IBM |
| Comparative Experimental Study of the Improved MOSFET Matching by Using the Hexagonal Layout Style |
| Prof., Salvador Pinillos Gimenez, Centro Universitario da FEI |
| Monolithic 3D (M3D) Reconfigurable Logic Applications Using Extremely-Low-Power Electron Devices |
| Prof., Woo Young Choi, Sogang University |
| Analyzing the carrier mobility in two-dimensional MoS2 transistors |
| Prof., Xinran Wang, Nanjing University |
| Design Technology Co-optimization for Disruptive Patterning Schemes |
| Professor, Puneet Gupta, UCLA |
| TBD |
| Donis Flagello, CEO, Nikron Research America |
| Molecular Force Modeling of Lithography |
| Zhimin Zhu, Senior Scientist, Brewster Science |
| The Insertion of extreme ultraviolet lithography (EUVL) from patterning perspective |
| Weimin Gao, Senior cooperate application engineer, Synopsys |
| Design Technology Co-optimization for Disruptive Patterning Schemes |
| Professor, Puneet Gupta, UCLA |
| Patterning Technology Inflections for the 10n and Beyond Logic Nodes |
| Richard Wise, Managing Director, Lam Research, USA |
| Advanced Plasma Etch technology and Applications |
| Ganming Zhao, Senior Director, Applied Materials, China |
| Atomic Precision Etching using a Low Electron Temperature Plasma |
| Shahid Rauf, Senior Director, Applied Materials, Inc. |
| Advanced technology for sub-10nm Patterning |
| Naoki Inagaki, Project Leader and Director, Tokyo Electron Limited |
| Interconnect Reliability Challenges for the 7nm Node and Below |
| Tony Oates, IEEE Fellow; Senior Director, TSMC |
| More-Moore Versus More-than-Moore and a Future of 50 Billion Connected Devices |
| Aaron Voon-Yew Thean, Vice President of Logic Technologies, Professor in National Singapore University, IMEC |
| Enabling Complex Patterning Through Materials Innovation |
| Mark Saly, Manager, COE in Chemistry, AMAT |
| Oxide based thin films for Current and Emerging Logic Applications |
| Vijay Narayanan, Manager and distinguished research staff member, IBM |
| Method of Forming a More Robust Sidewall Spacer with Lower k (Dielectric Constant) Value |
| Tao Han, Member of Technical Staff, Globalfoundries Inc. US |
| 14 nm/10 nm Logic Node – Issues and Key Enabling Technologies |
| Dr.Reza Arghavani, Managing Director of Technology, Lam Research Corporation |
| The challenge of Si Development in the nanoscale era |
| Charles Chu, Engagement Director, PDF Solution |
| Review of thin film porosity characterization approaches |
| Konstantin P. Mogilnikov, Principal Scientist, Leuven Instruments Co. Ltd (Jiangsu) |
| Replacement Metal Gate (RMG) CMP for 14nm Transistor Scaling: Overview, Challenges and Opportunities |
| Hong Jin Kim, Advanced Module Engineering (AME), Globalfoundries |
| Abrasive Particle Trajectories and Material Removal Non-uniformity during Chemical Mechanical Polishing |
| V. Rastegar, Clarkson University |
| Chemical Mechanical Planarization – Building Stacked Devices |
| Viorel Balan, Univ. Grenoble Alpes |
| Challenges in CMP Defects of 7nm Device and its improvement opportunities |
| Dr. Ji Chul Yang, Senior Member of Technical Staff (SMTS) and CMP Representative of Future Technology Roadmap Team, Globalfoundries |
| Outsourced CMP for Rapid Development and Efficient Manufacturing |
| Robert L. Rhoades, CTO, Entrepix, Inc. |
| Nano Scale Interface Control for 28nm Cu CMP through Cu/Barrier Slurries |
| Zhijie Zhang, Semiconductor Manufacturing North China (Beijing) Corp. |
| Cu CMP Dishing and Erosion Optimization for Hybrid Bonding Technology |
| GuangYi Wang, Wuhan Xinxin Semiconductor Manufacturing Co. Anji Microelectronics Co., Ltd. |
| A New Acidic ILD Slurry Formulation for Advanced CMP |
| Yi Guo, Dow Electronic Materials |
| Time-dependent Clustering Model for Dielectric Breakdown with Variability |
| Ernest Wu, STSM, IEEE Fellow, IBM T. J. Watson Research Center, USA |
| New Approach For Full Chip Electrical Reliability Verification |
| Frank Feng, Manager, Mentor Graphics, USA |
| On the use of conductive atomic force microscopy to monitor resistive switching |
| Mario Lanza, Young 1000 Talent Professor, Soochow University |
| Physical Failure Analysis of Semiconductor Devices by Electron Probing and Transmission Electron Microscopy |
| Dr. John Li, Principal Member Technical Staff, Globalfoundries, USA |
| Key technologies and application demonstrations of 3D heterogeneous integration and FOWLP |
| Professor, Kuan-Neng Chen, Prof, NCTU |
| Process and Equipment Technology for Advanced Packaging |
| Dr. Arvind Sundarraja/Scott Lin, Head, Asia Pacific Product Development Center, Applied Materials |
| TBD |
| Yifan Guo, Dr., VP Technology, ASE |
| Fanout Technology and Development |
| Scott Sikorski, Dr., VP Technology, SCL |
| Role of Advanced Packaging in IC Scaling and Homogeneous and Heterogeneous Integration |
| Hamid Azimi, Dr., VP, Intel |
| 3D & MEMS Vertical MEMS Probe Technology For Advanced Packaging |
| Amy Leong, VP Marketing, Formfactor |
| Neutral Beam Technology for Future Nano-devices |
| Professor, Seiji Samukawa, IFS Tohoku University |
| Extreme Miniaturization of Passive Electronic Devices by Self-Rolled-up Membrane Nanotechnology |
| Professor, Xiuling Li, UIUC |
| NOVEL ELECTRON DEVICES BASED ON LASER SCRIBED GRAPHENE |
| Professor, Lu-Qi Tao, Tsinghua University |
| Operation Fundamentals in Backend memories: programming window, retention and endurance |
| Luca Perniola, CEA Tech |
| TBD |
| Professor, Shaojun Wei, Tsinghua University |
提前注册并付费 | 注册费 | |
听众 | 人民币 3,700 | 人民币 4,200 |
学生（持有效证件） | 人民币 2,100 | 人民币 2,600 |
晚宴（3月12日18:00-20:00） | 人民币 600 | 人民币 800 |
